Как я провел воскресенье

Смастерил примерчик для вводного курса по микроконтроллерам и FPGA и проинструктировал как использовать Microchip MPLAB X и Xilinx ISE профессоршу из Казахстана, которая гостит в Калифорнии:

Сходил со старшим сыном в зоопарк (не в Сан-Франциско, а в Окленде):

В зоопарке интересные парковые розы

Потом пошли в ресторан. На первое сьел жареные устрицы:

на второе сьел равиоли с артишоками и крабами. одновременно читал интернет с дискуссиями, был ли Голодомор на Украине геноцидом:

На обратном пути попал в пробку и увидел, как везли вот такую машину:

Приложение: код примерчика на Верилоге:

Зеленая плата — Digilent Cmod S6 с Xilinx Spartan-6 FPGA (xc6slx4, package cpg196, speed -2)

module clock_divider
(
    input        clock,
    input        reset,
    output       clock_for_debouncing,
    output       clock_for_display
);

    reg [19:0] counter;

    always @(posedge clock)
    begin
        if (reset)
            counter <= 0;
        else
            counter <= counter + 1;
    end

    // clock is 8 MHz
    // clock_for_debouncing is 8 MHz / 2 ** (16 + 1) ~ 61 Hz
    // clock_for_display    is 8 MHz / 2 ** (12 + 1) ~ 977 Hz

    assign clock_for_debouncing = counter [16];
    assign clock_for_display    = counter [12];

endmodule

module debouncer
(
    input      clock,
    input      clock_for_debouncing,
    input      reset,
    input      button,
    output reg push
);

    reg [2:0] samples;

    always @(posedge clock_for_debouncing)
    begin
        if (reset)
            samples <= 0;
        else
            samples <= { samples [1:0], button };
    end

    wire current = & samples;
    reg  previous;

    always @(posedge clock)
    begin
        if (reset)
        begin
            previous <= 0;
            push     <= 0;
        end
        else
        begin
            previous <= current;
            push     <= { previous, current } == 2'b01;
        end
    end

endmodule

module display
(
    input             clock,
    input             reset,
    input      [15:0] number,
    output reg [ 6:0] seven_segments,
    output reg [ 3:0] cathodes
);

    function [6:0] bcd_to_seg (input [3:0] bcd);

        case (bcd)
        'h0: bcd_to_seg = 'b0111111;  // g f e d c b a
        'h1: bcd_to_seg = 'b0000110;
        'h2: bcd_to_seg = 'b1011011;  //   --a--
        'h3: bcd_to_seg = 'b1001111;  //  |     |
        'h4: bcd_to_seg = 'b1100110;  //  f     b
        'h5: bcd_to_seg = 'b1101101;  //  |     |
        'h6: bcd_to_seg = 'b1111101;  //   --g--
        'h7: bcd_to_seg = 'b0000111;  //  |     |
        'h8: bcd_to_seg = 'b1111111;  //  e     c
        'h9: bcd_to_seg = 'b1100111;  //  |     |
        'ha: bcd_to_seg = 'b1110111;  //   --d-- 
        'hb: bcd_to_seg = 'b1111100;
        'hc: bcd_to_seg = 'b0111001;
        'hd: bcd_to_seg = 'b1011110;
        'he: bcd_to_seg = 'b1111001;
        'hf: bcd_to_seg = 'b1110001;
        endcase

    endfunction

    reg [1:0] i;

    always @(posedge clock or posedge reset)
    begin
        if (reset)
        begin
            i <= 0;

            seven_segments <= bcd_to_seg (0);
            cathodes       <= 'b0000;
        end
        else
        begin
            seven_segments <= bcd_to_seg (number [i * 4 +: 4]);
            cathodes       <= ~ (1 << i);

            i <= i + 1;
        end
    end

endmodule

module raw_and_debounced
(
    input        CLK,         // FPGA_GCLK, 8MHz
    input        CLK_LFC,     // FPGA_LFC, 1 Hz

    output       LED_0,
    output       LED_1,
    output       LED_2,
    output       LED_3,

    input        BTN_0,
    input        BTN_1,

    // DEPP interface

    // input        DEPP_ASTB,   // Address strobe
    // input        DEPP_DSTB,   // Data strobe
    // input        DEPP_WRITE,  // Write enable (write operation = 0, read operation = 1)
    // output       DEPP_WAIT,   // Ready 
    // inout  [7:0] DBUS,

    // General purpose I/O

    output [7:0] PORTA,
    output [7:0] PORTB,
    output [6:0] PORTC,
    output [7:0] PORTD,
    input  [7:0] PORTE,
    output [6:0] PORTF
);

    assign PORTB = 'hff;
    assign PORTC = 'h7f;
    assign PORTD = 'hff;
    
    wire clock = CLK;
    wire reset = BTN_0;

    wire clock_for_debouncing;
    wire clock_for_display;

    clock_divider clock_divider
    (
        .clock                 ( clock                ),
        .reset                 ( reset                ),
        .clock_for_debouncing  ( clock_for_debouncing ),
        .clock_for_display     ( clock_for_display    )
    );

    wire raw_button                = ~ PORTE [7];
    wire pre_debounced_button      = ~ PORTE [6];
    wire posedge_debounced_button;

    wire on_board_button = ~ BTN_1;

    debouncer debouncer
    (
        .clock                 ( clock                    ),
        .clock_for_debouncing  ( clock_for_debouncing     ),
        .reset                 ( reset                    ),
        .button                ( pre_debounced_button     ),
        .push                  ( posedge_debounced_button )
    );

    reg   [15:0] number;
    wire  [ 6:0] seven_segments;
    wire  [ 3:0] cathodes;

    display display
    (
        .clock           ( clock_for_display ),
        .reset           ( reset             ),
        .number          ( number            ),
        .seven_segments  ( seven_segments    ),
        .cathodes        ( cathodes          )
    );

    // g f e d c b a
    
    //   --a--
    //  |     |
    //  f     b
    //  |     |
    //   --g--
    //  |     |
    //  e     c
    //  |     |
    //   --d-- 
		  
    assign PORTA [0] = seven_segments [4]; // E  1
    assign PORTA [1] = seven_segments [3]; // D  2
    assign PORTA [2] = 0;                  // .  3
    assign PORTA [3] = seven_segments [2]; // C  4
    assign PORTA [4] = seven_segments [6]; // G  5
    assign PORTA [5] = seven_segments [1]; // B  7
    assign PORTA [6] = seven_segments [5]; // F 10
    assign PORTA [7] = seven_segments [0]; // A 11

    assign PORTF = { 4'b1111, cathodes };

    assign LED_0 = 0; // raw_button;
    assign LED_1 = 0; // pre_debounced_button;
    assign LED_2 = 0;
    assign LED_3 = 0;

    reg prev_raw_button;

    always @(posedge CLK)
    begin
        if (reset)
            prev_raw_button <= 0;
        else
            prev_raw_button <= raw_button;
    end
	 
    wire posedge_raw_button = ~ prev_raw_button & raw_button;

    always @(posedge CLK)
    begin
        if (reset)
            number = 0;
        else if (posedge_raw_button | posedge_debounced_button)
            number = number + 1;
    end

endmodule

# cmods6.ucf

#FPGA_GCLK
NET "CLK" LOC = "N8" | IOSTANDARD = LVCMOS33;

#CLK_LFC
NET "CLK_LFC" LOC = "N7" | IOSTANDARD = LVCMOS33;

#BTNs
NET "BTN_0" LOC = "P8" | IOSTANDARD = LVCMOS33;
NET "BTN_1" LOC = "P9" | IOSTANDARD = LVCMOS33;

#LEDs
NET "LED_0" LOC = "N3" | IOSTANDARD = LVCMOS33;
NET "LED_1" LOC = "P3" | IOSTANDARD = LVCMOS33;
NET "LED_2" LOC = "N4" | IOSTANDARD = LVCMOS33;
NET "LED_3" LOC = "P4" | IOSTANDARD = LVCMOS33;

#DEPP Signals
#NET "DEPP_WAIT" LOC = "B6" | IOSTANDARD = LVCMOS33;
#NET "DEPP_ASTB" LOC = "A6" | IOSTANDARD = LVCMOS33;
#NET "DEPP_DSTB" LOC = "B7" | IOSTANDARD = LVCMOS33;
#NET "DEPP_WRITE" LOC = "A7" | IOSTANDARD = LVCMOS33;
#NET "DBUS<0>" LOC = "B9" | IOSTANDARD = LVCMOS33;
#NET "DBUS<1>" LOC = "A9" | IOSTANDARD = LVCMOS33;
#NET "DBUS<2>" LOC = "B10" | IOSTANDARD = LVCMOS33;
#NET "DBUS<3>" LOC = "A10" | IOSTANDARD = LVCMOS33;
#NET "DBUS<4>" LOC = "B11" | IOSTANDARD = LVCMOS33;
#NET "DBUS<5>" LOC = "A11" | IOSTANDARD = LVCMOS33;
#NET "DBUS<6>" LOC = "B12" | IOSTANDARD = LVCMOS33;
#NET "DBUS<7>" LOC = "A12" | IOSTANDARD = LVCMOS33;

#IO PORTs

#A
NET "PORTA<0>" LOC = "P5" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTA<1>" LOC = "N5" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTA<2>" LOC = "N6" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTA<3>" LOC = "P7" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTA<4>" LOC = "P12" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTA<5>" LOC = "N12" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTA<6>" LOC = "L14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTA<7>" LOC = "L13" | IOSTANDARD = LVCMOS33 | PULLUP;

#B
NET "PORTB<0>" LOC = "K14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTB<1>" LOC = "K13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTB<2>" LOC = "J14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTB<3>" LOC = "J13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTB<4>" LOC = "H14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTB<5>" LOC = "H13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTB<6>" LOC = "F14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTB<7>" LOC = "F13" | IOSTANDARD = LVCMOS33 | PULLUP;

#C
NET "PORTC<0>" LOC = "G14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTC<1>" LOC = "G13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTC<2>" LOC = "E14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTC<3>" LOC = "E13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTC<4>" LOC = "D14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTC<5>" LOC = "D13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTC<6>" LOC = "C13" | IOSTANDARD = LVCMOS33 | PULLUP;

#D
NET "PORTD<0>" LOC = "A3" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTD<1>" LOC = "B3" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTD<2>" LOC = "A2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTD<3>" LOC = "B1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTD<4>" LOC = "C1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTD<5>" LOC = "D1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTD<6>" LOC = "D2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTD<7>" LOC = "E1" | IOSTANDARD = LVCMOS33 | PULLUP;

#E
NET "PORTE<0>" LOC = "E2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTE<1>" LOC = "F1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTE<2>" LOC = "F2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTE<3>" LOC = "H1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTE<4>" LOC = "H2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTE<5>" LOC = "G1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTE<6>" LOC = "G2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTE<7>" LOC = "J1" | IOSTANDARD = LVCMOS33 | PULLUP;

#F
NET "PORTF<0>" LOC = "J2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTF<1>" LOC = "K1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTF<2>" LOC = "K2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTF<3>" LOC = "L1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTF<4>" LOC = "L2" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTF<5>" LOC = "M1" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "PORTF<6>" LOC = "M2" | IOSTANDARD = LVCMOS33 | PULLUP;

источник — panchulpanchul 
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